Altium

Design Rule Verification Report

Date:		2025/4/1
Time:		11:18:05
Elapsed Time:		00:00:01
Filename:		C:\Users\root\Documents\Altium\Blueberry\Blueberry.PcbDoc

Warnings:		0
Rule Violations:		1

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=3.5mil) (All),(All)	0
Clearance Constraint (Gap=3.5mil) (All),(inpolygon)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=3mil) (Max=100mil) (Preferred=4mil) (All)	0
Routing Topology Rule(Topology=Shortest) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Hole Size Constraint (Min=1mil) (Max=150mil) (All)	0
Hole To Hole Clearance (Gap=0mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Silk To Solder Mask (Clearance=0mil) (IsPad),(All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	1
Board Clearance Constraint (Gap=0mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	1

Net Antennae (Tolerance=0mil) (All)
Net Antennae: Via (1716.19mil,1231.58mil) from Top Layer to Bottom Layer